PCB structural design is a critical stage determining the mechanical reliability, manufacturability, thermal performance and EMC performance of circuit boards. The core objectives are mechanical compliance, rational layer stackup, partitioned component placement, plus balanced consideration of thermal design, safety standards and DFM (Design for Manufacturability).

I. Mechanical Structure Design (Board Outline, Mounting & Panelization)

1. Outline & Dimensions

The board outline must strictly comply with ID/MD drawings with a tolerance of ±0.2 mm; ±0.1 mm for gold finger regions.

Board corners shall adopt rounded fillets with R ≥ 0.5 mm to prevent stress cracking; add process borders ≥ 5 mm in width if required.

Common board thickness options: 0.8 / 1.0 / 1.2 / 1.6 / 2.0 mm, selected according to current load and mechanical stiffness requirements.

2. Positioning & Mounting Holes

Tooling Holes (NPTH, Non-Plated Through Hole): diameter ≥ 2.0 mm, center-to-board-edge distance ≥ 3 mm.

Screw Mount Holes:

PTH (Plated Through Hole): Hole diameter = screw diameter + 0.5 mm (e.g., M2 screw → minimum hole diameter ≥ 2.5 mm).

NPTH (Non-Plated Through Hole): Hole diameter = screw diameter + 1.0 mm.

Maintain a keep-out zone ≥ 3 mm around connectors and IC packages to avoid enclosure mechanical interference.

3. Panelization & Depaneling (Key DFM Item)

V‑Cut: Linear depaneling. Remain 1/3 of original board thickness (0.8 mm thick board retains residual thickness of 0.25–0.3 mm).

Mouse Bite (Breakaway Tab): Hole diameter 0.6–1.0 mm, hole pitch 1.0–1.5 mm; arrange 3–5 holes per side with connecting bridge width ≥ 2.0 mm.

CNC Routing Depaneling: Slot width ≥ 1.6 mm; place no components within routing slots.

II. Layer Stackup Design (Performance Foundation)

Core Principles

Prioritize ground planes: Deploy at least one solid continuous ground plane to provide low-impedance return paths and shielding.

Signal layers adjacent to reference planes: Every signal layer shall sit next to ground or power planes.

Tight coupling between power and ground: Form planar capacitance and reduce power supply impedance.

Symmetrical stackup: Prevent board warpage with balanced copper thickness distribution.

Route high-speed / high-frequency traces on inner layers (stripline) to minimize electromagnetic radiation.

Typical Stackup Examples

4‑Layer (Recommended): Top Signal → GND → Power → Bottom Signal

4‑Layer (Dual Ground, Optimized EMC): Top → GND → GND → Bottom

6‑Layer: Top → GND → Signal 1 → Signal 2 → Power → Bottom (or dual-ground variants)

III. Placement Design (Functional Partition & Signal Flow)

1. Functional Partitioning (Mandatory Isolation)

Partition by functional modules: Power domain, digital domain, analog domain, RF domain, interface domain.

Analog & Digital Circuits: Physically separated; ground planes connected only via single-point link or ferrite bead.

High Voltage & Low Voltage: Satisfy safety creepage & clearance requirements; add isolation slots when necessary.

High-speed & Low-speed Circuits: Concentrate high-speed circuits away from noise sources.

2. Placement Rules for Critical Components

Interfaces (USB, Ethernet, Power Connectors): Place near board edges for convenient plug-in operation.

Core ICs (MCU / FPGA): Position centrally to shorten critical signal paths.

Crystals: Mount closely to target ICs; prohibit routing underneath; shell connected to ground.

Decoupling Capacitors: Adjacent to IC power pins (spacing ≤ 3 mm).

Heat-generating devices (MOSFET, LDO): Distribute placement and reserve unobstructed thermal flow paths.

Thermal-sensitive components (electrolytic capacitors, oscillators): Keep away from heat sources.

IV. Thermal Design

High-power devices: Adopt cross-shaped thermal relief pads and deploy thermal via arrays.

Large-area copper pours: Use ground / power copper areas as heat conduction channels.

Heatsinks: Reserve mounting footprint and vertical clearance, guarantee unobstructed airflow channels.

V. Key Design Points for Safety Standards & EMC

Creepage distance & Clearance: Comply with standards such as IEC 60950.

Isolation Zones: Apply slotting / cutouts in high-voltage regions; cutouts permitted underneath optocouplers.

Grounding Architecture: Digital GND / Analog GND / Power GND connected via single-point connection or ferrite beads.

Shielding: Install shielding cans over RF and sensitive circuits with multi-point grounding.

VI. DFM (Design for Manufacturability) Guidelines

Minimum trace width & trace spacing: Comply with factory process capability (general specification ≥ 4/4 mil).

Vias: Hole diameter ≥ 0.2 mm, pad diameter ≥ 0.4 mm; avoid via-in-pad unless specified.

Silkscreen: Clear printing without overlapping pads; include version number, board name and barcode.

Surface Finish: Select ENIG, HASL, OSP or other finishes according to application demands.

VII. Structural Design Workflow

Confirm mechanical constraints: board outline, mounting holes, height-restricted zones, interface positions.

Determine layer count and complete layer stackup definition.

Pre-placement partitioning: power circuits, digital circuits, analog circuits, RF circuits.

Locate critical components: interfaces, main ICs, crystals, power devices.

Refine component layout, thermal layout and safety isolation treatment.

Develop panelization & depaneling scheme.

DFM & structural review: tolerance verification, interference check, manufacturing feasibility validation.