Q1: How to handle theoretical conflicts in practical routing?

Basically, splitting and separating analog and digital grounds is the right approach. Keep signal traces from crossing split regions (moat), and don't let the return current paths of power and signals become unnecessarily large.

A crystal oscillator is an analog positive-feedback circuit. For stable oscillation, loop gain and phase specifications must be met. This analog oscillation is easily disturbed—even guard traces may not fully isolate interference—and if the crystal is placed too far, noise on the ground plane can also disturb the positive-feedback oscillator. So keep the crystal as close to the chip as possible.

High-speed routing and EMI requirements do conflict in many ways. The basic rule is: the resistors, capacitors, or ferrite beads added for EMI suppression must not violate the signal's electrical specifications. So first try to solve or reduce EMI through routing and [stackup design] PCB techniques (e.g., running high-speed signals on inner layers), and only use resistors, capacitors, or ferrite beads as a last resort to minimize impact on the signal.

Q2: How to resolve the conflict between manual and auto routing for high-speed signals?

Most modern router tools support constraint settings to control routing patterns and via count. However, routing engine capabilities and constraint options vary widely across EDA vendors—for example, whether the tool provides enough constraints to control serpentine tuning and differential pair spacing directly affects whether auto-routed results match the designer's intent.

In addition, how easily you can manually adjust routes depends heavily on the router's push-and-shove capability—for traces, vias, and even copper pours. Choosing a router with a strong routing engine is the fundamental solution.

Q3: In high-speed PCB design, empty areas on signal layers can be copper-poured. How should copper pours on multiple signal layers be allocated to ground and power?

In most cases, empty-area copper pours should connect to ground. When pouring copper next to high-speed signal traces, pay attention to the spacing, because the pour will slightly lower the trace's characteristic impedance. Also avoid affecting the impedance of other layers, e.g., in a dual stripline structure.

Q4: Can signals on top of a power plane be modeled as microstrip for impedance calculation? Can signals between power and ground planes be modeled as stripline?

Yes. When calculating characteristic impedance, both the power plane and ground plane must be treated as reference planes. For example, on a 4-layer board with stackup "Top – Power – GND – Bottom," the top-layer traces use a microstrip model referenced to the power plane.

Q5: Can software-generated test points on high-density PCBs generally meet mass-production test requirements?

Whether auto-generated test points satisfy test needs depends on whether the test-point design rules comply with the test fixture requirements. In addition, if routing is very dense and test-point rules are strict, the tool may not be able to add test points to every net segment, in which case manual addition is required.

Q6: Does adding test points affect high-speed signal quality?

It depends on how the test points are added and how fast the signal is. In general, don't reuse existing vias or DIP pins as test points. You can add the test point directly on the trace, or stub out a short branch. The first is equivalent to adding a small capacitance on the line; the second adds a short stub.

Both have some effect on high-speed signals, depending on the signal frequency and edge rate; the impact can be evaluated by simulation. In principle, test points should be as small as possible (while still meeting fixture requirements) and stubs as short as possible.

Q7: In a system of multiple PCBs, how should the grounds between boards be connected?

When signals or power between boards are active—e.g., board A sends power or signals to board B—an equal amount of current must return from the ground plane to board A (Kirchhoff's current law). The return current flows through the lowest-impedance path. Therefore, at every power/signal interconnect interface, don't assign too few pins to ground; this lowers impedance and ground-plane noise.

You can also analyze the entire current loop, especially for high-current paths, and adjust the ground plane or grounding scheme to direct current flow (e.g., create a low-impedance path so most current takes that route), reducing interference with other sensitive signals.

Q8: What are the principles for choosing PCB-to-chassis ground points?

The principle is to use chassis ground to provide a low-impedance path for return current and to control its routing. For example, near high-frequency devices or clock generators, you can use mounting screws to connect the PCB ground plane to the chassis, minimizing the current loop area and thus reducing EMI.

Q9: What should be debugged first on a new board?

For digital circuits, confirm three things in order:

1. Verify all power supply rails reach their specified values (some multi-rail systems also require specific power-up sequencing and ramp rates);

2. Verify all clock frequencies are running and clock edges are free of non-monotonic behavior;

3. Verify reset signals meet specifications.

If all of these are normal, the chip should output its first cycle; then continue debugging according to system operation principles and bus protocol.

Q10: When board size is fixed and more functions require higher routing density—which can increase crosstalk and force narrower traces—what techniques exist for high-speed (>100 MHz) high-density PCB design?

In high-speed, high-density PCB design, crosstalk is a key concern because it strongly affects timing and signal integrity. Key points:

- Control continuous, matched characteristic impedance. Typical spacing is twice trace width; simulate to find the minimum acceptable spacing based on timing and SI impact (results vary by chip).

- Choose appropriate termination. Avoid routing adjacent layers in the same direction, and never route traces directly overlapping between layers—this causes more crosstalk than same-layer adjacent traces.

- Use blind/buried vias to free up routing area (this increases PCB fabrication cost).

- In practice, perfect parallelism and length matching are hard to achieve, but still try as much as possible.

Q11: Why do layer-change vias cause signal integrity issues in high-speed designs? How to optimize via design? (Added)

Vias are essential connections in multilayer PCBs, but their parasitic capacitance and inductance cause impedance discontinuity at high speeds: at low frequencies capacitance dominates (capacitive), above ~5 GHz inductance dominates (inductive), leading to reflection, resonant notches, and other SI problems. Above 1 GHz, via parasitics can no longer be ignored; the longer the via stub, the worse the high-frequency resonance and reflection.

Juehui Weiye Circuit Recommendations

- Minimize layer changes for critical high-speed signals; when a change is unavoidable, add stitching vias near the signal via to maintain a continuous return path.

- For signals above 5–10 Gbps, consider backdrilling to remove excessive via stubs.

- Tune via impedance through antipad sizing and 3D simulation; in high-speed differential pairs, use the same number and symmetric placement of vias on both traces.

Q12: What are the key points for differential signal routing? (Added)

High-speed signals are often routed as differential pairs (e.g., USB, PCIe, SATA, CAN) to suppress common-mode noise and improve noise immunity. Key routing rules:

- Length matching: Both traces of a pair must be equal in length to keep intra-pair skew within tolerance (typical: ±5 mil within a pair).

- Constant spacing: Maintain uniform spacing throughout to keep differential impedance stable (e.g., ~90 Ω for USB, ~100 Ω for PCIe); never route other signals between the pair.

- Symmetry: When layer changes are needed, use the same number of symmetrically placed vias on both traces to preserve differential coupling.

- Serpentine compensation: When length tuning requires serpentine, avoid sharp angles (prefer 45° miter or arcs); keep serpentine amplitude within twice the trace spacing to avoid disrupting differential coupling, local impedance discontinuities, and radiated resonance.

About Juehui Weiye Circuit

Good high-speed design isn't just about "getting the layout right"—it's about "making it manufacturable and reliable." Shenzhen Juehui Weiye Circuit Co., Ltd. has specialized in PCB and PCBA for over a decade, focusing on high-precision multilayer boards, HDI blind/buried via boards, and high-frequency high-speed boards. We support impedance control, backdrill, blind/buried vias and other high-speed processes, and provide one-stop service from DFM design review, PCB fabrication, SMT assembly to finished-product testing and assembly. Whether you need high-speed design prototyping or stable volume production, share your Gerber files and stackup requirements with us—our engineering team will verify every process step.