Back-drilling is currently the mainstream process to remove redundant copper on via walls, shorten stub length and improve signal integrity. Nevertheless, micro-hole back-drilling in BGA areas features smaller hole diameters and limited chip evacuation space. Compared with conventional large-aperture back-drilling, it has higher technical barriers and is prone to defects such as inner burrs, hole blockage, hole position offset and uncontrolled back-drilling depth. This remains a tough challenge in high-speed PCB manufacturing.

Based on full-process experimental research on micro-hole back-drilling, Juehui Weiye Circuit carries out mechanism analysis on typical defects of BGA micro-hole back-drilling and DOE parameter verification. We have optimized a stable and controllable new micro-hole back-drilling process to meet the mass production requirements of high-speed PCBs.

1. Core Existing Defects of Micro-hole Back-drilling

For high-frequency and high-speed PCB applications above 10Gbps, the stub length is generally required to be controlled within 0.25 mm. The processing difficulties of BGA micro-hole back-drilling fall into four categories:

1. Burrs and hole blockage after back-drilling: The intersecting copper layer is suspended during back-drilling and tends to be torn to form copper burrs. The small aperture of micro-holes limits chip evacuation, leading to accumulation of copper dust and direct hole blockage. The combination of micro-hole and back-drilling further amplifies these defects.

2. Hole position accuracy deviation of back-drilled holes: Micro-hole back-drilling is a secondary drilling operation. The small drill bit diameter easily causes hole position offset during processing, resulting in misalignment between the back-drilled hole and the original via.

3. Insufficient depth accuracy of back-drilling: Insufficient back-drilling depth leaves stubs incompletely removed; excessive depth will damage functional signal layers, making depth control difficult.

4. Difficulty in removing via copper: The via copper thickness of conventional processes can reach 15 μm. For small holes, it is hard for back-drilling to cut through the via wall copper in one pass, and residual copper debris induces burrs.

2. Root Cause Analysis of Micro-hole Back-drilling Defects

The biggest difference between micro-hole back-drilling and ordinary back-drilling lies in the smaller processing aperture, which is the fundamental reason for the high incidence of burrs and hole blockage:

- The small aperture restricts the space of drill flutes, greatly reducing chip removal capacity.

- Uneven stress during small-aperture drilling easily tears the inner hole wall and generates copper burrs. Meanwhile, poor dust suction leads to dust accumulation and hole blockage.

- The two traditional back-drilling workflows both have drawbacks:

 - Workflow 1 (Inner Layer → Lamination → Drilling → Copper Deposition & Plating → AOI → Dry Film): Severe burr and blockage problems occur during micro-hole back-drilling, preventing stable mass production.

 - Workflow 2 (Inner Layer → Lamination → Drilling → Copper Deposition & Plating → Pattern Plating → Tin Plating → Back-drilling → Development & Alkaline Etching): An extra etching step is added, yet dust adheres to the inner wall of micro-holes and cannot be removed by etching, resulting in a still high defect rate.

To tackle these pain points, we have designed an improved workflow:

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> Inner Layer → Lamination → Drilling → Primary Plating → Back-drilling → Secondary Plating → Outer Layer Patterning → Subsequent Standard Processes

Primary plating precisely controls via copper thickness and reduces cutting resistance for back-drilling. Combined with secondary plating and post-processing, this solution fundamentally solves burr and blockage issues in micro-hole back-drilling.

3. Process Test and Result Verification

We built a test model and conducted multi-dimensional tests covering hole position accuracy, alignment between back-drilled holes and vias, DOE verification of processing parameters and reliability, to validate the stability of the new process.

1. Via Hole Position Accuracy Test

Two sizes of vias (0.25 mm and 0.30 mm) were selected and fully inspected by a hole position scanner.

The maximum deviation for both apertures is 50 μm, with process capability Cpk＞1.33. Excellent hole position accuracy meets the baseline requirements for BGA micro-hole fabrication.

2. Alignment Accuracy between Back-drilled Holes and Vias

Metallographic cross-section sampling and inspection were performed. For 0.45 mm and 0.50 mm back-drilled holes matched with corresponding vias, the alignment deviation between back-drilled holes and original vias is ≤0.10 mm and Cpk≥1.33, which meets alignment specifications.

Analysis of variance shows that **back-drill aperture, back-drill depth and pitch have no significant impact on alignment accuracy. Processing quality is mainly determined by the process scheme and drilling machine parameters.

3. DOE Test to Determine Optimal Back-drilling Parameters (for Burr & Blockage Control)

Full inspection via visual check and 10× optical magnification was adopted. A DOE orthogonal test was designed with variables including spindle speed (S), feed rate (F) and retract rate (U).

✅ Optimal parameter set:

Spindle Speed S = 65000 r/min, Feed Rate F = 36 mm/min, Retract Rate U = 337 mm/min

With these parameters, the hole blockage rate can be stably controlled within 0~0.5%.

Mass verification: Matched combinations of 0.25 mm via + 0.45 mm back-drill and 0.30 mm via + 0.50 mm back-drill achieve zero burr and zero blockage defects in volume production.

4. Product Reliability Verification

SMT reflow soldering conditions were simulated: peak temperature 260℃, dwelling at 255℃ for 20~30 seconds. After 5 consecutive reflow cycles, no failures such as hole wall delamination or hole cracking were observed. The reliability meets the long-term service standards for high-speed PCBs and computing boards.

4. Conclusion & Application Value

This research on micro-hole back-drilling verifies that besides aperture limitation, the alignment accuracy between back-drilled holes and vias is the core factor causing inner burrs and hole blockage.

By adjusting process sequence, optimizing copper control logic of electroplating and matching dedicated drilling parameters, this improved micro-hole back-drilling process successfully addresses the industry pain points of BGA micro-hole back-drilling:

- ✅ Compatible with AI computing boards, high-speed switches and high-frequency communication PCBs, supporting 112G/224G PAM4 high-speed signal integrity;

- ✅ Greatly reduces stub-related defects and mitigates risks of signal loss, crosstalk and bit errors;

- ✅ Stable process suitable for mass production and custom high-density HDI high-speed PCB fabrication.

If you require prototype or medium-batch production of high-speed computing PCBs and BGA micro-hole back-drilling boards, Juehui Weiye Circuit provides supporting process solutions for signal integrity. We welcome technical discussion and drawing evaluation.